Explicit Dynamic Scheduling: A Practical Micro-Data ow Architecture

This paper introduces Explicit Dynamic Scheduling (EDS), a practical implementation of dataaow on a chip. By combining RISC design principles with well-known compiler dependence analysis techniques, EDS combines a straightforward hardware design, suitable for high speed implementation, with the performance advantages of dataaow at the instruction level. EDS uniies pipeline and memory latency tolerance in a single paradigm, and is able to exploit parallelism at ner grain sizes than recent hybrid dataaow approaches. The scope of parallelism exploited by EDS is limited to inner loops and ne-grained parallelism, leaving coarse-grained parallelism to be exploited between processors with explicit scheduling software. This leads to a more straightforward hardware implementation than traditional micro-dataaow schemes. The dynamic scheduling provided by EDS has measurable performance advantages over superscalar and superpipelined RISC processors relying on static instruction scheduling.